VLSI-Simplified

Few simple VHDL codes

Combinational circuits 1. Unsigned 8-bit adder. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity adder is port(A,B : in std_logic_vector(7 downto 0); SUM : out std_logic_vector(7 downto 0)); end adder; architecture archi of adder is begin SUM <= A...

Verification in VLSI

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General view: • Verification : an unavoidable effort. • It never gives result but gives assurity of correct result. • A mother testing food before serving to baby. IEEE definition: “Confirmation by examination and provisions of objective evidence...