Combinational circuits

1. Unsigned 8-bit adder.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity adder is

port(A,B : in std_logic_vector(7 downto 0);

SUM : out std_logic_vector(7 downto 0));

end adder;

architecture archi of adder is

begin

SUM <= A + B;

end archi;

2. Unsigned 8-bit subtractor.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity subtr is

port(A,B : in std_logic_vector(7 downto 0);

RES : out std_logic_vector(7 downto 0));

end subtr;

architecture archi of subtr is

begin

RES <= A - B;

end archi;

3. Unsigned 8-bit adder with carry in.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity adder is

port(A,B : in std_logic_vector(7 downto 0);

CI : in std_logic;

SUM : out std_logic_vector(7 downto 0));

end adder;

architecture archi of adder is

begin

SUM <= A + B + CI;

end archi;

4. Decoder  1:8

library ieee;

use ieee.std_logic_1164.all;

entity dec is

port (sel: in std_logic_vector (2 downto 0);

res: out std_logic_vector (7 downto 0));

end dec;

architecture archi of dec is

begin

res <= "00000001" when sel = "000" else

"00000010" when sel = "001" else

"00000100" when sel = "010" else

"00001000" when sel = "011" else

"00010000" when sel = "100" else

"00100000" when sel = "101" else

"01000000" when sel = "110" else

"10000000";

end archi;

5.Priority encoder 1:9

library ieee;

use ieee.std_logic_1164.all;

entity priority is

port ( sel : in std_logic_vector (7 downto 0);

code :out std_logic_vector (2 downto 0));

end priority;

architecture archi of priority is

begin

code <= "000" when sel(0) = '1' else

"001" when sel(1) = '1' else

"010" when sel(2) = '1' else

"011" when sel(3) = '1' else

"100" when sel(4) = '1' else

"101" when sel(5) = '1' else

"110" when sel(6) = '1' else

"111" when sel(7) = '1' else

"---";

end archi;

6. 8-bit Comparator  (>,=):

Following is the VHDL code for an unsigned 8-bit greater or equal

comparator.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity compar is

port(A,B : in std_logic_vector(7 downto 0);

CMP : out std_logic);

end compar;

architecture archi of compar is

begin

CMP <= '1' when A >= B

else '0';

end archi;

7. Different ways of writing same logic : Multiplexer 

1. Mux using 'with'

library ieee;

     use ieee.std_logic_1164.all; 

entity mux1 is

     port (

         din_0   :in  std_logic;-- Mux first input

         din_1   :in  std_logic;-- Mux Second input

         sel     :in  std_logic;-- Select input

         mux_out :out std_logic -- Mux output

     );

 end entity;

 architecture behavior of mux_using_with is

 begin

     with (sel) select

     mux_out <= din_0 when '0',

                din_1 when others;         

 end architecture;

2. Mux using 'when'

library ieee;

     use ieee.std_logic_1164.all; 

 entity mux2 is

     port (

         din_0   :in  std_logic;-- Mux first input

         din_1   :in  std_logic;-- Mux Second input

         sel     :in  std_logic;-- Select input

         mux_out :out std_logic -- Mux output 

    );

 end entity; 

 architecture behavior of mux_using_when is

 begin

     mux_out <= din_0 when (sel = '0') else

                din_1;         

 end architecture;

3. Mux using 'if'

library ieee;

    use ieee.std_logic_1164.all; 

 entity mux3 is

     port (

         din_0   :in  std_logic;-- Mux first input

         din_1   :in  std_logic;-- Mux Second input

         sel     :in  std_logic;-- Select input

         mux_out :out std_logic -- Mux output 

     );

 end entity; 

 architecture behavior of mux_using_if is 

 begin

     MUX:

     process (sel, din_0, din_1) begin

        if (sel = '0') then

             mux_out <= din_0;

         else

             mux_out <= din_1;

         end if;

     end process;

 end architecture;

4. Mux using 'if'

library ieee;

    use ieee.std_logic_1164.all;

entity mux4 is

     port (

         din_0   :in  std_logic;-- Mux first input

         din_1   :in  std_logic;-- Mux Second input

         sel     :in  std_logic;-- Select input

        mux_out :out std_logic -- Mux output 

     );

 end entity;

architecture behavior of mux_using_case is 

 begin

     MUX:

     process (sel, din_0, din_1) begin

         case sel is

             when '0'    => mux_out <= din_0;

             when others => mux_out <= din_1;

         end case;

     end process;

 end architecture;

8. parity generator: 4-bit

Behavioral model

entity PARITY is

port(V: in BIT_VECTOR(3 downto 0);

   EVEN:out BIT);

end PARITY;

architecture PARITY_BEHAVIORAL of PARITY is

begin

process(V)

variable NR_1: NATURAL;

begin

NR_1:=0;

for I in 3 downto 0 loop

if V(I)='1' then

NR_1:=NR_1+1;

end if;

end loop;

if NR_1 mod 2 = 0 then

EVEN <= '1' after 2.5 ns;

else

EVEN <= '0' after 2.5 ns;

end if;

end process;

end PARITY_BEHAVIORAL;

is Kuchcinski (LTH)

Structural model



use WORK.all;

architecture PARITY_STRUCTURAL of PARITY is

component XOR_GATE

port(X,Y: in BIT; Z: out BIT);

end component;

component INV

generic(DEL: TIME);

port(X: in BIT; Z: out BIT);

end component;

signal T1, T2, T3: BIT;

begin

XOR1: XOR_GATE portmap (V(0), V(1), T1);

XOR2: XOR_GATE portmap (V(2), V(3), T2);

XOR3: XOR_GATE portmap (T1, T2, T3);

INV1: INV

generic map (0.5 ns)

port map (T3, EVEN);

end PRITY_STRUCTURAL;

Sequential circuits

1. D-latch 

library ieee;

    use ieee.std_logic_1164.all;

 entity dlatch_reset is

    port (   data  :in  std_logic;-- Data input

            en    :in  std_logic;-- Enable input

            reset :in  std_logic;-- Reset input

            q     :out std_logic -- Q output

        );

 end entity;

architecture rtl of dlatch_reset is

begin

     process (en, reset, data) begin

         if (reset = '0') then

               q <= '0';

         elsif (en = '1') then

         q <= data;

        end if;

    end process;

 end architecture;
2. Up-counter: 8-bit

library ieee;

    use ieee.std_logic_1164.all;

     use ieee.std_logic_unsigned.all;

entity up_counter is

   port (

      cout   :out std_logic_vector (7 downto 0); -- Output of the counter

       enable :in  std_logic;                     -- Enable counting

       clk    :in  std_logic;                     -- Input clock

      reset  :in  std_logic                      -- Input reset

     );

end entity;

architecture rtl of up_counter is

    signal count :std_logic_vector (7 downto 0);

begin

     process (clk, reset) begin

         if (reset = '1') then

            count <= (others=>'0');

         elsif (rising_edge(clk)) then

            if (enable = '1') then

                count <= count + 1;

            end if;

       end if;

   end process;

    cout <= count;

end architecture;
2. Up-down counter: 8-bit

library ieee;
     use ieee.std_logic_1164.all;
     use ieee.std_logic_unsigned.all;
 entity up_down_counter is
   port (
     cout    :out std_logic_vector (7 downto 0);
     up_down :in  std_logic;                   -- up_down control for counter
     clk     :in  std_logic;                   -- Input clock
     reset   :in  std_logic                    -- Input reset
   );
 end entity;
 architecture rtl of up_down_counter is
     signal count :std_logic_vector (7 downto 0);
 begin
     process (clk, reset) begin
         if (reset = '1') then
             count <= (others=>'0');
         elsif (rising_edge(clk)) then
            if (up_down = '1') then
                count <= count + 1;
             else
                 count <= count - 1;
             end if;
         end if;
     end process;
     cout <= count;
 end architecture;




All the best for further coding with this background !

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General view:

• Verification : an unavoidable effort.

• It never gives result but gives assurity of correct result.

• A mother testing food before serving to baby.

IEEE definition:

“Confirmation by examination and provisions of objective evidence that specified requirements have been fulfilled.”

Verification in VLSI Field:

• 70% of the total efforts in ASIC cycle

• Number of verification engineer is twice the number of RTL design engineer

• Test benches makes up 80% of the total code volume.

(Bug: Pantium bug costs to nearly 4.75 million dollar.)

Impact of Incomplete Verification

• Costly re-spin(s)

• Companies may miss out market window

• Large companies can have reputation at stake

        – e.g. Pentium Bug

• Smaller companies can have hard to recover financial implications

• For start-ups, their existence itself can be at stake!

Verification Techniques

• Simulation

• Formal Verification (comparison)

• Static Timing Analysis

Simulator:

Simulator makes a computing model of the

circuit, executes the model for a set of

input signals (stimuli, patterns, or vector),

and verifies the output signals.

Formal Verification

• Can be used to verify a design against a reference design as it progresses through the different levels of abstraction

• Verifies functionality without test vectors•

• obtaining a complete FSM description of the system.

• FSM (Discrete functions) can be represented conveniently by BDDs (binary decision diagram) and its extension MDDs (multi-valued decision diagram)

Static Timing Analysis

• Inputs: – Netlist, library models of the cells and constraints (clock period, skew, setup and hold time…)

• Outputs:– Delay through the combinational logic

• Basic concepts:

– Look for the longest  topological path

– Discard it if it is false

Verification Languages

•“e”

• Vera

• Suger

• System – C

• System – Verilog Language

• verilog

VERIFICATION REUSE

• verification consuming 60-80% of the manpower on complex chip projects

• improving verification productivity is an economic necessity Verification reuse directly addresses higher productivity

• all components be built and packaged uniformly.

• efficient integration of reusable, plug-and play verification components

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