Verification in VLSI

General view:

• Verification : an unavoidable effort.

• It never gives result but gives assurity of correct result.

• A mother testing food before serving to baby.

IEEE definition:

“Confirmation by examination and provisions of objective evidence that specified requirements have been fulfilled.”

Verification in VLSI Field:

• 70% of the total efforts in ASIC cycle

• Number of verification engineer is twice the number of RTL design engineer

• Test benches makes up 80% of the total code volume.

(Bug: Pantium bug costs to nearly 4.75 million dollar.)

Impact of Incomplete Verification

• Costly re-spin(s)

• Companies may miss out market window

• Large companies can have reputation at stake

        – e.g. Pentium Bug

• Smaller companies can have hard to recover financial implications

• For start-ups, their existence itself can be at stake!

Verification Techniques

• Simulation

• Formal Verification (comparison)

• Static Timing Analysis

Simulator:

Simulator makes a computing model of the

circuit, executes the model for a set of

input signals (stimuli, patterns, or vector),

and verifies the output signals.

Formal Verification

• Can be used to verify a design against a reference design as it progresses through the different levels of abstraction

• Verifies functionality without test vectors•

• obtaining a complete FSM description of the system.

• FSM (Discrete functions) can be represented conveniently by BDDs (binary decision diagram) and its extension MDDs (multi-valued decision diagram)

Static Timing Analysis

• Inputs: – Netlist, library models of the cells and constraints (clock period, skew, setup and hold time…)

• Outputs:– Delay through the combinational logic

• Basic concepts:

– Look for the longest  topological path

– Discard it if it is false

Verification Languages

•“e”

• Vera

• Suger

• System – C

• System – Verilog Language

• verilog

VERIFICATION REUSE

• verification consuming 60-80% of the manpower on complex chip projects

• improving verification productivity is an economic necessity Verification reuse directly addresses higher productivity

• all components be built and packaged uniformly.

• efficient integration of reusable, plug-and play verification components