Getting started with VHDL codes

To code in any Hardware description language, one must know the digital design aspects. Let's start with a the simplest circuit - a Full adder. Following figure shows its logic-gate implementation.

The VHDL Code can be constructed either by following its functionality or by looking at its structure in above circuit.(Behavioural/ Data flow modelling & Structural modelling respectively)

Sample Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity F_adder is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           sum : out  STD_LOGIC;
           carry : out  STD_LOGIC);
end F_adder;
architecture Behavioral of F_adder is
begin
sum <= (a xor b) xor cin;
carry <= (a and b)or (cin and (a xor b));
end Behavioral;

Functional Simulation Result:


Post-route Simulation results:

 Note: These simulation results are drawn by using Xilinx ISE design suit.